N/C = no change, the latch will stay in whatever state it was in. The truth table for a gated SR latch is the following: S When the enable input is high, the S (set) and R (reset) inputs pass through and latch behaves as the SR latch describes in previous two sections. When the enable input is low, the latch will not respond to any changes in inputs S (set) and R (reset). The configuration would look like the image presented in figure 5 below. If we add a couple of AND gates to the SR latch, we can control, via a third input known as вЂњenableвЂќ, when the latch will respond to the inputs S (set) and R (reset). Block diagram SR latch active low Gated SR latches Figure 4 is an illustration of a Block diagram SR latch active low.ДЇigure 4. We can represent the active low SR latch with a block diagram instead of the more complicated NAND gate schematic each time we build or represent this latch. Again, notice that when SвЂ™ and RвЂ™ are вЂњlowвЂќ, the latch is set and reset. When SвЂ™=0, RвЂ™=1, the latch is in the set state. When SвЂ™=1, RвЂ™=0, the latch is in the reset state. The only time when the outputs change is when one of the inputs momentarily goes low thus the active low SR latch. You notice from the truth table that if the inputs remain low, the output Q (and QвЂ™) remains unchanged. The truth table for the active low SR latch is the following: S Active high SR gates can be made from two NAND gates with 1 input of each fed from the output of another. Block diagram SR latch active highДЇigure 3 below is a latch that will only become activated when one of the inputs momentarily goes low. When S=0, R=1, the latch is in the reset state.Д®ach time we build or represent this latch, we can represent the Active high SR latch with a block diagram instead of the more complicated NOR gate schematic.ДЇigure 2. When S=1, R=0, the latch is in the set state. The only time the outputs change is when one of the inputs momentarily goes high, thus the active high SR latch, this is illustrated in figure 2 below. You notice from the truth table that if the inputs remain low, the output Q (and QвЂ™) remain unchanged. N/c = no change, the latch will stay in whatever state it was in. The truth table for the active high SR latch is the following: S Figure 1 is an illustration of an Active High SR Latch. Active high SR gates can be made from two NOR gates with 1 input of each fed from the output of another. This is a latch that will only become activated when one of the inputs momentarily goes high. We will discuss the operation of SR (set-reset) latches, gated SR latches and D latch. Latches are in a family of devices known as multivibrators, that is, they are bistable devices that can store 2 stable states. A latch is a logic that can вЂњstoreвЂќ a value of 1 or 0 (or a single bit) indefinitely. Our first adventure into sequential logic is to study latches. We will also discuss positive and negative edge triggering (trigger) which clocks the way in which the input state changes in sequential circuits.

The difference between flip-flops and latches is the way in which the logic changes the state of their outputs. In this module, we will discuss the building blocks of sequential logic which includes latches, and flip-flops. It can be said that sequential logic is logic with memory. In sequential logic, the output not only depends on the current state of the inputs as combinatorial logic but also on the state of the inputs stored in the past.

This module will focus on sequential logic. How are flip-flops used in counting and frequency divider circuits?.What is the difference between combinatorial logic and sequential logic?.Explain the operation of synchronous counters.Explain the operation of asynchronous вЂњdivide byвЂќ counters.Describe the concept of counting in digital circuits.Describe several applications of flip-flops.

Explain the operation of J/K flip-flops.Explain the operation of the gated SR latch.Define positive and negative edge triggering.Explain the difference between combinatorial logic and sequential logic.

Negative edge triggered flip flop